This invention relates to a semiconductor memory device.
In particular this invention relates to a semiconductor memory device, comprising an array of rows and columns of field effect transistors (FETs) providing memory locations for storing data, each FET having a conduction channel region extending between first and second main electrodes and a gate electrode for controlling conduction along the conduction channel region, and row and column conductors, the gate electrodes of the FETs in each row being connected to a respective row conductor and the first and second main electrode of the FETs in each column being connected to respective adjacent column conductors so that the second main electrodes of the FETs in one column are connected to the first electrodes of the FETs in any adjacent column. Circuitry is provided storing data at and reading data from the memory locations.
U.S. Pat. No. 4,451,904 describes such a so-called floating or virtual earth memory array in which the field effect transistors are in the form of floating gate MOS (FAMOS) transistors. U.S. Pat. No. 4,173,791 (11/6/79) describes a virtual earth memory array in which the transistors are in the form of PINOS transistors, that is insulated gate field effect transistors where the gate insulating region is provided by a layer of silicon nitride followed by a layer of silicon oxide. Data is stored by the injection of hot electrons from the drain of the transistor into the floating gate in the case of U.S. Pat. No. 4,451,904 and into the silicon nitride layer in the case of U.S. Pat. No. 4,173,791.
In such devices each transistor defines a unique memory location and in order to access a particular memory location, that is a particular transistor, an appropriate voltage is applied to the row conductor connected to the row of transistors containing the desired memory location while a voltage difference is applied across the column conductors connected to the two main electrodes of the selected transistor. So as to avoid accessing the other transistors in the same row, the column conductors adjacent the column conductor connected to one of the first and second main electrodes of the selected transistor are held at the same potential as that column conductor while the column conductors adjacent the column conductor connected to the other of the first and second main electrodes of the selected transistor are held at the same potential as that conductor. Thus, a potential difference only exists between the first and second electrodes of the transistors in the selected column.
Although such a semiconductor memory device and the above-described access method are acceptable for a bulk crystalline semiconductor structure, they are not suitable for use in thin film technology because hot electron injection cannot be used as a mechanism for data storage.